A soft error mitigation technique for constrained gate-level designs
نویسندگان
چکیده
منابع مشابه
An approximated soft error analysis technique for gate-level designs
As the semi-conductor technology advances, the evaluation of soft error hardness for modern electrical and electronic devices becomes more generalized. Related studies have mainly focused on the soft error rate analysis of both combinational and sequential logic circuits, which includes techniques for dynamic simulation, and pathbased statistical estimation. In particular, non-dynamic approache...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2008
ISSN: 1349-2543
DOI: 10.1587/elex.5.698